An energy efficiency 4-bit multiplier with two-phase non-overlap clock driven charge recovery logic

Yimeng Zhang*, Leona Okamura, Tsutomu Yoshihara

*この研究の対応する著者

    研究成果: Article査読

    7 被引用数 (Scopus)

    抄録

    A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. PBL belongs to boost logic family, which includes boost logic, enhanced boost logic and subthreshold boost logic. In this paper, PBL has been compared with other charge-recovery logic technologies. To demonstrate the performance of PBL structure, a 4-bit pipeline multiplier is designed and fabricated with 0.18 μm CMOS process technology. The simulation results indicate that the 4-bit multiplier can work at a frequency of 1.8 GHz, while the measurement of test chip is at operation frequency of 161 MHz, and the power dissipation at 161 MHz is 772 μW.

    本文言語English
    ページ(範囲)605-612
    ページ数8
    ジャーナルIEICE Transactions on Electronics
    E94-C
    4
    DOI
    出版ステータスPublished - 2011 4

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • 電子材料、光学材料、および磁性材料

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