An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

    研究成果: Article

    1 引用 (Scopus)

    抄録

    In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods

    元の言語English
    ページ(範囲)1376-1391
    ページ数16
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E98A
    発行部数7
    DOI
    出版物ステータスPublished - 2015 7 1

    Fingerprint

    High-level Synthesis
    Energy Efficient
    Clocks
    Interconnect
    Energy Saving
    Interconnection
    Placement
    Energy Consumption
    Energy conservation
    Synchronization
    Chip
    Energy utilization
    Integrate
    Entire
    Cycle
    Configuration
    Communication
    Experimental Results
    Design
    High level synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    これを引用

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    AU - Shi, Youhua

    AU - Usami, Kimiyoshi

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

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