抄録
A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.
本文言語 | English |
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ページ(範囲) | 388-393 |
ページ数 | 6 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 24 |
号 | 2 |
DOI | |
出版ステータス | Published - 1989 4月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学