An FPGA-based 4K UHDTV H.264/AVC video decoder

Yue Pan, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

    本文言語English
    ホスト出版物のタイトルElectronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
    DOI
    出版ステータスPublished - 2013
    イベント2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013 - San Jose, CA
    継続期間: 2013 7 152013 7 19

    Other

    Other2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
    CitySan Jose, CA
    Period13/7/1513/7/19

    ASJC Scopus subject areas

    • Computer Graphics and Computer-Aided Design
    • Computer Vision and Pattern Recognition

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