An FPGA implementation method based on distributed-register architectures

研究成果: Article

抄録

In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.

元の言語English
ページ(範囲)38-41
ページ数4
ジャーナルIPSJ Transactions on System LSI Design Methodology
12
DOI
出版物ステータスPublished - 2019 2 1

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Field programmable gate arrays (FPGA)
Networks (circuits)

Keywords

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering

    これを引用

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    abstract = "In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21{\%} faster than the circuit based on a traditional architecture.",
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    AU - Kawamura, Kazushi

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

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    AB - In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.

    KW - Distributed-register architecture

    KW - FPGA implementation

    KW - High-level synthesis

    KW - Interconnection delay

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