In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.
|ジャーナル||IPSJ Transactions on System LSI Design Methodology|
|出版物ステータス||Published - 2019 2 1|
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering