An independent bandwidth reduction device for HEVC VLSI video system

Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

FRC (frame re-compression) is a kind of widely used technique in reducing the SDRAM (synchronous dynamic random access memory) bandwidth of HEVC video system. However, in previous research works, FRC imposes requirements on accessing pattern and hence its usage are only limited in HEVC video codecs. While in a typical HEVC VLSI video system, there exists many other video IPs with high bandwidth requirements. Therefore, in this article, we propose a new FRC architecture to overcome the limitation and make it applicable to all the video IPs in a HEVC VLSI video system, which raises the overall bandwidth reduction rate of the whole video system. Our proposal has two points: firstly we propose a system internal bus based FRC architecture, which is independent, transparent, and easily connected to all other video IPs. Secondly, we propose a FA (freely access) scheme to remove the requirements on access pattern in previous work. By using this proposal, the bandwidth reduction rate in our VLSI video system model is raised from 92.4% to 69.6%.

本文言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
出版社Institute of Electrical and Electronics Engineers Inc.
ページ609-612
ページ数4
2015-July
ISBN(印刷版)9781479983919
DOI
出版ステータスPublished - 2015 7 27
イベントIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
継続期間: 2015 5 242015 5 27

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period15/5/2415/5/27

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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