An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

本文言語English
ホスト出版物のタイトルProceedings of the ASP-DAC 2006
ホスト出版物のサブタイトルAsia and South Pacific Design Automation Conference 2006
出版社Institute of Electrical and Electronics Engineers Inc.
ページ594-599
ページ数6
ISBN(印刷版)0780394518, 9780780394513
DOI
出版ステータスPublished - 2006
イベントASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
継続期間: 2006 1 242006 1 27

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2006

Conference

ConferenceASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period06/1/2406/1/27

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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