TY - GEN
T1 - An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
AU - Kohara, Shunitsu
AU - Tomono, Naoki
AU - Uchida, Jumpei
AU - Miyaoka, Yuichiro
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2006
Y1 - 2006
N2 - In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.
AB - In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.
UR - http://www.scopus.com/inward/record.url?scp=33748606345&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748606345&partnerID=8YFLogxK
U2 - 10.1145/1118299.1118440
DO - 10.1145/1118299.1118440
M3 - Conference contribution
AN - SCOPUS:33748606345
SN - 0780394518
SN - 9780780394513
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 594
EP - 599
BT - Proceedings of the ASP-DAC 2006
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Y2 - 24 January 2006 through 27 January 2006
ER -