An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Shunitsu Kohara; Naoki Tomono; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1145/1118299.1118440

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

基幹理工学部

研究成果: Conference contribution

1 引用（Scopus）

抜粋

In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

元の言語	English
ホスト出版物のタイトル	Proceedings of the ASP-DAC 2006
ホスト出版物のサブタイトル	Asia and South Pacific Design Automation Conference 2006
出版者	Institute of Electrical and Electronics Engineers Inc.
ページ	594-599
ページ数	6
ISBN（印刷物）	0780394518, 9780780394513
DOI	https://doi.org/10.1145/1118299.1118440
出版物ステータス	Published - 2006
イベント	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan 継続期間: 2006 1 24 → 2006 1 27

出版物シリーズ

名前	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
巻	2006

Conference

Conference	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
国	Japan
市	Yokohama
期間	06/1/24 → 06/1/27

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

文献にアクセス

10.1145/1118299.1118440

フィンガープリント An interface-circuit synthesis method with configurable processor core in IP-based SoC designs' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

これを引用

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2006). An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ： Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 594-599). [1594750] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1118299.1118440

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. / Kohara, Shunitsu; Tomono, Naoki; Uchida, Jumpei; Miyaoka, Yuichiro; Togawa, Nozomu ; Yanagisawa, Masao; Ohtsuki, Tatsuo.

Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. p. 594-599 1594750 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻 2006).

研究成果: Conference contribution

Kohara, S, Tomono, N, Uchida, J, Miyaoka, Y, Togawa, N , Yanagisawa, M & Ohtsuki, T 2006, An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ： Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006., 1594750, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 巻. 2006, Institute of Electrical and Electronics Engineers Inc., pp. 594-599, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, Japan, 06/1/24. https://doi.org/10.1145/1118299.1118440

Kohara S, Tomono N, Uchida J, Miyaoka Y, Togawa N , Yanagisawa M その他. An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ： Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc. 2006. p. 594-599. 1594750. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1145/1118299.1118440

Kohara, Shunitsu ; Tomono, Naoki ; Uchida, Jumpei ; Miyaoka, Yuichiro ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. pp. 594-599 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{ce7419b345f3487a8bd870936f702832,

title = "An interface-circuit synthesis method with configurable processor core in IP-based SoC designs",

abstract = "In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.",

author = "Shunitsu Kohara and Naoki Tomono and Jumpei Uchida and Yuichiro Miyaoka and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",

year = "2006",

doi = "10.1145/1118299.1118440",

language = "English",

isbn = "0780394518",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "594--599",

booktitle = "Proceedings of the ASP-DAC 2006",

note = "ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 ; Conference date: 24-01-2006 Through 27-01-2006",

}

TY - GEN

T1 - An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

AU - Kohara, Shunitsu

AU - Tomono, Naoki

AU - Uchida, Jumpei

AU - Miyaoka, Yuichiro

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2006

Y1 - 2006

N2 - In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

AB - In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

UR - http://www.scopus.com/inward/record.url?scp=33748606345&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748606345&partnerID=8YFLogxK

U2 - 10.1145/1118299.1118440

DO - 10.1145/1118299.1118440

M3 - Conference contribution

AN - SCOPUS:33748606345

SN - 0780394518

SN - 9780780394513

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 594

EP - 599

BT - Proceedings of the ASP-DAC 2006

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006

Y2 - 24 January 2006 through 27 January 2006

ER -