抄録
In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| ページ | 594-599 |
| ページ数 | 6 |
| 巻 | 2006 |
| 出版物ステータス | Published - 2006 |
| イベント | ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama 継続期間: 2006 1 24 → 2006 1 27 |
Other
| Other | ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 |
|---|---|
| 市 | Yokohama |
| 期間 | 06/1/24 → 06/1/27 |
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ASJC Scopus subject areas
- Engineering(all)
これを引用
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. / Kohara, Shunitsu; Tomono, Naoki; Uchida, Jumpei; Miyaoka, Yuichiro; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2006 2006. p. 594-599 1594750.研究成果: Conference contribution
}
TY - GEN
T1 - An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
AU - Kohara, Shunitsu
AU - Tomono, Naoki
AU - Uchida, Jumpei
AU - Miyaoka, Yuichiro
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2006
Y1 - 2006
N2 - In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.
AB - In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.
UR - http://www.scopus.com/inward/record.url?scp=33748606345&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748606345&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33748606345
SN - 0780394518
SN - 9780780394513
VL - 2006
SP - 594
EP - 599
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ER -