An Ising model mapping to solve rectangle packing problem

Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

11 被引用数 (Scopus)

抄録

Floorplanning of modules has been a significant role in VLSI design automation and it can be formulated as the 'Rectangle Packing Problem.' Ising model-based computers (or annealing machines) are the type of a non-von Neumann computer and recently expected to solve combinatorial optimization problems efficiently. In this paper, we propose a mapping of 'Rectangle Packing Problem' for solving it by the annealing machines. In our proposed mapping, a sequence-pair is represented on an Ising model. Our proposed approach maps a 'Rectangle Packing Problem' with N rectangles onto a 3N3-spin logical Ising model. Experimental results demonstrate that through the proposed approach we can solve the problem with 18 rectangles at the maximum on a fully-connected annealing machine and the problem with three rectangles at the maximum on 20k-spin CMOS annealing machine.

本文言語English
ホスト出版物のタイトル2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1-4
ページ数4
ISBN(電子版)9781538642603
DOI
出版ステータスPublished - 2018 6 5
イベント2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China
継続期間: 2018 4 162018 4 19

出版物シリーズ

名前2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
国/地域Taiwan, Province of China
CityHsinchu
Period18/4/1618/4/19

ASJC Scopus subject areas

  • 安全性、リスク、信頼性、品質管理
  • 制御と最適化
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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