An Ising model mapping to solve rectangle packing problem

Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

1 引用 (Scopus)

抄録

Floorplanning of modules has been a significant role in VLSI design automation and it can be formulated as the 'Rectangle Packing Problem.' Ising model-based computers (or annealing machines) are the type of a non-von Neumann computer and recently expected to solve combinatorial optimization problems efficiently. In this paper, we propose a mapping of 'Rectangle Packing Problem' for solving it by the annealing machines. In our proposed mapping, a sequence-pair is represented on an Ising model. Our proposed approach maps a 'Rectangle Packing Problem' with N rectangles onto a 3N3-spin logical Ising model. Experimental results demonstrate that through the proposed approach we can solve the problem with 18 rectangles at the maximum on a fully-connected annealing machine and the problem with three rectangles at the maximum on 20k-spin CMOS annealing machine.

元の言語English
ホスト出版物のタイトル2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
出版者Institute of Electrical and Electronics Engineers Inc.
ページ1-4
ページ数4
ISBN(電子版)9781538642603
DOI
出版物ステータスPublished - 2018 6 5
イベント2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China
継続期間: 2018 4 162018 4 19

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Taiwan, Province of China
Hsinchu
期間18/4/1618/4/19

Fingerprint

Ising model
Packing Problem
Rectangle
Ising Model
Annealing
Combinatorial optimization
Floorplanning
Design Automation
VLSI Design
Automation
Combinatorial Optimization Problem
Model-based
Module
Experimental Results
Demonstrate

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Control and Optimization
  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Terada, K., Oku, D., Kanamaru, S., Tanaka, S., Hayashi, M., Yamaoka, M., ... Togawa, N. (2018). An Ising model mapping to solve rectangle packing problem. : 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373233

An Ising model mapping to solve rectangle packing problem. / Terada, Kotaro; Oku, Daisuke; Kanamaru, Sho; Tanaka, Shu; Hayashi, Masato; Yamaoka, Masanao; Yanagisawa, Masao; Togawa, Nozomu.

2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.

研究成果: Conference contribution

Terada, K, Oku, D, Kanamaru, S, Tanaka, S, Hayashi, M, Yamaoka, M, Yanagisawa, M & Togawa, N 2018, An Ising model mapping to solve rectangle packing problem. : 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, Province of China, 18/4/16. https://doi.org/10.1109/VLSI-DAT.2018.8373233
Terada K, Oku D, Kanamaru S, Tanaka S, Hayashi M, Yamaoka M その他. An Ising model mapping to solve rectangle packing problem. : 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4 https://doi.org/10.1109/VLSI-DAT.2018.8373233
Terada, Kotaro ; Oku, Daisuke ; Kanamaru, Sho ; Tanaka, Shu ; Hayashi, Masato ; Yamaoka, Masanao ; Yanagisawa, Masao ; Togawa, Nozomu. / An Ising model mapping to solve rectangle packing problem. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4
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