In the High Efficiency Video Coding (HEVC), block sizes for hybrid-prediction and residual encoding are recursively selected by using a quadtree structure. This technique requires enormous computational complexity. Nevertheless, the exhaustive quadtree-based partition is not always necessary. This paper fully utilizes all-zero residual blocks to accelerate HEVC encoding process. A near-sufficient condition is derived to detect variable-sized all-zero blocks. For these blocks, DCT and quantization can be skipped. Moreover, a novel PU pruning technique based on allzero block is presented to constrain prediction units (PU) which have little contribution to RD performance. Experiments on a wide range of videos show that proposed scheme can reduce up to 73.42% and an average of 53.37% computational complexity for HEVC encoder with only trivial loss in PSNR and rate.
|ホスト出版物のタイトル||IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|
|出版ステータス||Published - 2012|
|イベント||2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung|
継続期間: 2012 12 2 → 2012 12 5
|Other||2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012|
|Period||12/12/2 → 12/12/5|
ASJC Scopus subject areas