The huge SDRAM bandwidth requirement is an architectural bottleneck of video decoders. Besides the large amounts of data transmission cycles, many extra overhead (up to over 50%) are incurred by the ACTIVE or PRECHARGE (A\P) operations in conventional SDRAM controllers. In this paper, we propose an optimized SDRAM controller, which can improve the bandwidth efficiency by eliminating most of the extra overhead. An access management scheme that enables consecutive data transmission is employed to reduce the need of A\P operations. In addition, a scheduler is designed to hide the latency for A\P operations. Experimental result shows that the SDRAM controller is able to meet the bandwidth requirement of real-time decoding 1080P H.264 video streams, at less than 100Mhz with 32-bit DDR SDRAM.
|ホスト出版物のタイトル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版ステータス||Published - 2008|
|イベント||2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA|
継続期間: 2008 5 18 → 2008 5 21
|Other||2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008|
|Period||08/5/18 → 08/5/21|
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