An SDRAM controller optimized for high definition video coding application

Jiayi Zhu, Peilin Liu, Dajiang Zhou

研究成果: Conference contribution

32 引用 (Scopus)

抜粋

The huge SDRAM bandwidth requirement is an architectural bottleneck of video decoders. Besides the large amounts of data transmission cycles, many extra overhead (up to over 50%) are incurred by the ACTIVE or PRECHARGE (A\P) operations in conventional SDRAM controllers. In this paper, we propose an optimized SDRAM controller, which can improve the bandwidth efficiency by eliminating most of the extra overhead. An access management scheme that enables consecutive data transmission is employed to reduce the need of A\P operations. In addition, a scheduler is designed to hide the latency for A\P operations. Experimental result shows that the SDRAM controller is able to meet the bandwidth requirement of real-time decoding 1080P H.264 video streams, at less than 100Mhz with 32-bit DDR SDRAM.

元の言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
ページ3518-3521
ページ数4
DOI
出版物ステータスPublished - 2008
外部発表Yes
イベント2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA
継続期間: 2008 5 182008 5 21

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Seattle, WA
期間08/5/1808/5/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • これを引用

    Zhu, J., Liu, P., & Zhou, D. (2008). An SDRAM controller optimized for high definition video coding application. : Proceedings - IEEE International Symposium on Circuits and Systems (pp. 3518-3521). [4542218] https://doi.org/10.1109/ISCAS.2008.4542218