Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultralow complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose an application specific instruction-set processor (ASIP) for ME. It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.