### 抜粋

In this paper, we propose the method for embedding the latch and the flip flop (FF) circuit to the universal logic circuit of Double Gate Carbon NanoTube Field Effect Transistor (DG-CNTFET) proposed in the previous work. Previously, 2-inputs universal logic circuit by 8 DG-CNTFET was proposed. If the embedding of flip flop to them is possible, the reconfigurable circuit which includes a state such as flip flop can be realized. The result of our research shows that SR-latch and D-latch with 3-inputs/state can be embedded within 2-inputs universal logic circuit. Thus it is shown that a D-FF can be embedded to two 2-inputs universal logic circuit.

元の言語 | English |
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ホスト出版物のタイトル | 2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2013 |

ページ | 148-152 |

ページ数 | 5 |

DOI | |

出版物ステータス | Published - 2013 12 9 |

外部発表 | Yes |

イベント | 14th IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, PACRIM 2013 - Vancouver, BC, Canada 継続期間: 2013 8 27 → 2013 8 29 |

### 出版物シリーズ

名前 | IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings |
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### Other

Other | 14th IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, PACRIM 2013 |
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国 | Canada |

市 | Vancouver, BC |

期間 | 13/8/27 → 13/8/29 |

### ASJC Scopus subject areas

- Signal Processing
- Computer Networks and Communications

## フィンガープリント An universal logic-circuit with flip flop circuit based on DG-CNTFET' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

## これを引用

*2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2013*(pp. 148-152). [6625465] (IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings). https://doi.org/10.1109/PACRIM.2013.6625465