An universal logic-circuit with flip flop circuit based on DG-CNTFET

Yasuyuki Miura, Hiroshi Ninomiya, Manabu Kobayashi, Shigeyoshi Watanabe

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

In this paper, we propose the method for embedding the latch and the flip flop (FF) circuit to the universal logic circuit of Double Gate Carbon NanoTube Field Effect Transistor (DG-CNTFET) proposed in the previous work. Previously, 2-inputs universal logic circuit by 8 DG-CNTFET was proposed. If the embedding of flip flop to them is possible, the reconfigurable circuit which includes a state such as flip flop can be realized. The result of our research shows that SR-latch and D-latch with 3-inputs/state can be embedded within 2-inputs universal logic circuit. Thus it is shown that a D-FF can be embedded to two 2-inputs universal logic circuit.

本文言語English
ホスト出版物のタイトル2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2013
ページ148-152
ページ数5
DOI
出版ステータスPublished - 2013
外部発表はい
イベント14th IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, PACRIM 2013 - Vancouver, BC, Canada
継続期間: 2013 8 272013 8 29

出版物シリーズ

名前IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Other

Other14th IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, PACRIM 2013
国/地域Canada
CityVancouver, BC
Period13/8/2713/8/29

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ ネットワークおよび通信

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