Analysis and reduction of SRAM PUF Bit Error Rate

Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu

研究成果: Conference contribution

3 引用 (Scopus)

抄録

Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

元の言語English
ホスト出版物のタイトル2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
出版者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781509039692
DOI
出版物ステータスPublished - 2017 6 5
イベント2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan, Province of China
継続期間: 2017 4 242017 4 27

Other

Other2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Taiwan, Province of China
Hsinchu
期間17/4/2417/4/27

Fingerprint

Static random access storage
Bit error rate
Transistors
Hardware security

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

これを引用

Shinohara, H., Zheng, B., Piao, Y., Liu, B., & Liu, S. (2017). Analysis and reduction of SRAM PUF Bit Error Rate. : 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 [7939688] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2017.7939688

Analysis and reduction of SRAM PUF Bit Error Rate. / Shinohara, Hirofumi; Zheng, Baikun; Piao, Yanhao; Liu, Bo; Liu, Shiyu.

2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7939688.

研究成果: Conference contribution

Shinohara, H, Zheng, B, Piao, Y, Liu, B & Liu, S 2017, Analysis and reduction of SRAM PUF Bit Error Rate. : 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017., 7939688, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, Province of China, 17/4/24. https://doi.org/10.1109/VLSI-DAT.2017.7939688
Shinohara H, Zheng B, Piao Y, Liu B, Liu S. Analysis and reduction of SRAM PUF Bit Error Rate. : 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7939688 https://doi.org/10.1109/VLSI-DAT.2017.7939688
Shinohara, Hirofumi ; Zheng, Baikun ; Piao, Yanhao ; Liu, Bo ; Liu, Shiyu. / Analysis and reduction of SRAM PUF Bit Error Rate. 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 2017.
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