Analysis and reduction of SRAM PUF Bit Error Rate

Hirofumi Shinohara; Baikun Zheng; Yanhao Piao; Bo Liu; Shiyu Liu

doi:10.1109/VLSI-DAT.2017.7939688

Analysis and reduction of SRAM PUF Bit Error Rate

Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu

大学院情報生産システム研究科

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

本文言語	English
ホスト出版物のタイトル	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781509039692
DOI	https://doi.org/10.1109/VLSI-DAT.2017.7939688
出版ステータス	Published - 2017 6 5
イベント	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan, Province of China 継続期間: 2017 4 24 → 2017 4 27

Other

Other	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Country	Taiwan, Province of China
City	Hsinchu
Period	17/4/24 → 17/4/27

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

文献へのアクセス

10.1109/VLSI-DAT.2017.7939688

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引用スタイル

Shinohara, H, Zheng, B, Piao, Y, Liu, B & Liu, S 2017, Analysis and reduction of SRAM PUF Bit Error Rate. in 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017., 7939688, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, Province of China, 17/4/24. https://doi.org/10.1109/VLSI-DAT.2017.7939688

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