Analysis of parasitic resistance effects in MOS LSI

Kenji Anami*, Masahiko Yoshimoto, Hirofumi Shinohara, Osamu Tomisawa, Takao Nakano

*この研究の対応する著者

研究成果: Article査読

抄録

This paper describes simplified analysis of the effects of transistor source and drain parasitic resistances and interconnect resistance in MOS LSI's, and their application to the circuit designs for MOS LSI circuits and mask patterns. Heretofore the analysis of parasitic resistance effects has been complex and could only be calculated numerically with circuit analysis programs. However, in this paper, a simple expression is given for the effect of the source and drain parasitic resistances by using a linear approximation to the MOS transistor drain i‐v characteristics. Furthermore, the delays caused by interconnection resistance are analyzed under assumptions that are actually obtained in practical LSI's. the rules for optimum design of the crossunders used frequently in LSI's are obtained using the result. Finally, experimental results from MOS transistors which agreed well with the source and drain parasitic resistance effect analysis. A ring oscillator experiment which also resulted in good agreement with the interconnect resistance delay analysis shows the applicability of both analysis methods.

本文言語English
ページ(範囲)106-113
ページ数8
ジャーナルElectronics and Communications in Japan (Part I: Communications)
66
10
DOI
出版ステータスPublished - 1983
外部発表はい

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学

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