Analytical model of static noise margin in CMOS SRAM for variation consideration

Hirofumi Shinohara*, Koji Nii, Hidetoshi Onodera

*この研究の対応する著者

研究成果: Article査読

1 被引用数 (Scopus)

抄録

An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

本文言語English
ページ(範囲)1488-1500
ページ数13
ジャーナルIEICE Transactions on Electronics
E91-C
9
DOI
出版ステータスPublished - 2008 9
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「Analytical model of static noise margin in CMOS SRAM for variation consideration」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル