Application-specific network-on-chip synthesis: Cluster generation and network component insertion

Wei Zhong*, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto

*この研究の対応する著者

研究成果

16 被引用数 (Scopus)

抄録

Network-on-Chips (NoCs) have emerged as a paradigm for designing scalable communication architecture for System-on-Chips (SoCs). In NoC, one of the key challenges is to design the most power-performance efficient NoC topology that satisfies the application characteristics. In this paper, we present a three-stage synthesis approach to solve this problem. First, we propose an algorithm [floor-planning integrated with cluster generation (FCG)] to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Then, based on the size of applications, an Integer Linear Programming (ILP) and a heuristic method (H) are also proposed to place switches and network interfaces on the floorplan. Finally, a power and timing aware path allocation algorithm (PA) is carried out to determine the connectivity across different switches. Experimental results show that, for small applications, the NoC topology synthesized by FIP (FCGILPPA) method can save 27.54% of power, 4% of hop-count and 66% of running time on average. And for large applications, FHP (FCGHPA) synthesis method can even save 31.77% of power, 29% of hop-count and 94.18% of running time on average.

本文言語English
ホスト出版物のタイトルProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
ページ144-149
ページ数6
DOI
出版ステータスPublished - 2011
イベント12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA
継続期間: 2011 3 142011 3 16

Other

Other12th International Symposium on Quality Electronic Design, ISQED 2011
CitySanta Clara, CA
Period11/3/1411/3/16

ASJC Scopus subject areas

  • 電子工学および電気工学

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