Application-specific shared last-level cache optimization for low-power embedded systems

Huatao Zhao, Jiongyao Ye, Xian Su, Takahiro Watanabe

研究成果: Conference contribution

抄録

Modern embedded systems favor the chip multiprocessor frame to achieve higher performance, but they are restricted by the inefficient cache hierarchies. Typically, the accessing interference and improper allocation in last-level cache (LLC) shared by multiprocessors cause significant energy consumption and performance depression. In this paper, we propose a configurable and partitioned cache hierarchy where an energy-efficient runtime mechanism can well manage the shared LLC to meet application programs. This mechanism utilizes the repeated behaviors in hot subroutines of application and selects the proper partition intervals. Then, a low-power metric based configurable scheme is employed to explore the optimal allocation of given cache resources. Thus, we can provide each core with the optimal allocation information to dynamically partition the shared LLC during runtime. Experimental results for a quad-core system using the SPEC2006 benchmarks show that the cache access energy can be reduced by on average 32.5 percent compared to the equal partition scheme only with 1.3 percent performance off.

本文言語English
ホスト出版物のタイトルConference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷版)9781479988938
DOI
出版ステータスPublished - 2015 8 6
イベント13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015 - Grenoble, France
継続期間: 2015 6 72015 6 10

Other

Other13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015
国/地域France
CityGrenoble
Period15/6/715/6/10

ASJC Scopus subject areas

  • 電子工学および電気工学

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