抄録
In this paper a new approach to the placement problem is introduced. The main idea is to take advantage of what one can do in linear placement in tackling the two-dimensional placement problem. The method consists of three distinct phases, namely: decomposition, linear placement, and iterative improvement. Each is clearly spelled out. Both constructive and iterative algorithms are developed. The complexity of computation is analyzed and the method has been tried with practical examples.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | IEEE Trans Circuits Syst |
| ページ | 208-214 |
| ページ数 | 7 |
| 巻 | CAS-25 |
| エディション | 4 |
| 出版物ステータス | Published - 1978 4 |
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ASJC Scopus subject areas
- Engineering(all)
これを引用
APPROACH TO THE TWO-DIMENSIONAL PLACEMENT PROBLEM IN CIRCUIT LAYOUT. / Goto, Satoshi; Kuh, Ernest S.
IEEE Trans Circuits Syst. 巻 CAS-25 4. 編 1978. p. 208-214.研究成果: Chapter
}
TY - CHAP
T1 - APPROACH TO THE TWO-DIMENSIONAL PLACEMENT PROBLEM IN CIRCUIT LAYOUT.
AU - Goto, Satoshi
AU - Kuh, Ernest S.
PY - 1978/4
Y1 - 1978/4
N2 - In this paper a new approach to the placement problem is introduced. The main idea is to take advantage of what one can do in linear placement in tackling the two-dimensional placement problem. The method consists of three distinct phases, namely: decomposition, linear placement, and iterative improvement. Each is clearly spelled out. Both constructive and iterative algorithms are developed. The complexity of computation is analyzed and the method has been tried with practical examples.
AB - In this paper a new approach to the placement problem is introduced. The main idea is to take advantage of what one can do in linear placement in tackling the two-dimensional placement problem. The method consists of three distinct phases, namely: decomposition, linear placement, and iterative improvement. Each is clearly spelled out. Both constructive and iterative algorithms are developed. The complexity of computation is analyzed and the method has been tried with practical examples.
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M3 - Chapter
AN - SCOPUS:0017959499
VL - CAS-25
SP - 208
EP - 214
BT - IEEE Trans Circuits Syst
ER -