Approximate multiplier using reordered 4-2 compressor with or-based error compensation

Yufeng Xu, Yi Guo, Shinji Kimura

研究成果: Conference contribution

抄録

Today, the approximate circuits have become an efficient solution for low power design on human related error-tolerant applications, such as multimedia, recognition and several signal processing. Approximate multipliers are believed to be an important key to make approximate arithmetic systems, and more area efficient multiplier is expected. The paper proposes a new ar-ea-efficient 4-2 compressor based on input reordering and OR-based error compensation. By the reordering, we can focus on just 2 of 4 inputs, and the compressor becomes very simple and less gates. Two multipliers are proposed with different accuracy based on reordered compressors with OR-based error compensation. The experimental results show that the proposed multipliers achieve high accuracy (98.7% and 97.39%) while reduce power consumption (by 44.72% and 45.95%) and area (by 31.72% and 34.85%). The proposed approximate multipliers are applied on image sharpening process and show high PSNR and SSIM.

本文言語English
ホスト出版物のタイトルProceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
編集者Fan Ye, Ting-Ao Tang
出版社IEEE Computer Society
ISBN(電子版)9781728107356
DOI
出版ステータスPublished - 2019 10
イベント13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China
継続期間: 2019 10 292019 11 1

出版物シリーズ

名前Proceedings of International Conference on ASIC
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

Conference

Conference13th IEEE International Conference on ASIC, ASICON 2019
CountryChina
CityChongqing
Period19/10/2919/11/1

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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