Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application

Yiqing Huang, Takeshi Ikenaga

研究成果: Conference contribution

抄録

This paper presents one compact propagate partial SAD (PPSAD) engine for H.264/AVC in HDTV application. Firstly, by using mode reduction technique, redundant registers in original PPSAD structure is removed. Secondly, circuit optimization is applied on the whole structure. Redundant adders within processing element (PE) and PE rows are removed. With TSMC 0.18um technology under worst case conditions (1.62V, 125°C), the proposed architecture can achieve 27.4% to 33.2% reduction of hardware and 11.7% saving in power consumption. When it is applied to parallel processing of HDTV 1080p real-time encoder, about 10k gates can be saved compared with previous design.

本文言語English
ホスト出版物のタイトル2009 International SoC Design Conference, ISOCC 2009
ページ365-368
ページ数4
DOI
出版ステータスPublished - 2009 12 1
イベント2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
継続期間: 2009 11 222009 11 24

出版物シリーズ

名前2009 International SoC Design Conference, ISOCC 2009

Conference

Conference2009 International SoC Design Conference, ISOCC 2009
国/地域Korea, Republic of
CityBusan
Period09/11/2209/11/24

ASJC Scopus subject areas

  • 電子工学および電気工学

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