Area/delay estimation for digital signal processor cores

Y. Miyaoka, Y. Kataoka, N. Togawa, M. Yanagisawa, T. Ohtsuki

研究成果: Conference contribution

6 引用 (Scopus)

抜粋

Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2ns when comparing estimated area and delay with logic-synthesized area and delay.

元の言語English
ホスト出版物のタイトルProceedings of the ASP-DAC 2001
ホスト出版物のサブタイトルAsia and South Pacific Design Automation Conference 2001
出版者Institute of Electrical and Electronics Engineers Inc.
ページ156-161
ページ数6
ISBN(電子版)0780366336
DOI
出版物ステータスPublished - 2001 1 1
イベントAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
継続期間: 2001 1 302001 2 2

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Japan
Yokohama
期間01/1/3001/2/2

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • これを引用

    Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2001). Area/delay estimation for digital signal processor cores. : Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 156-161). [913297] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913297