Implementation of floating-point arithmetic functions is an essential task in high-level synthesis (HLS). However, most of the existing HLS EDA tools cannot well synthesize floating-point functions. In this paper, we present an automatic method to implement general floating-point functions using piecewise polynomial approximation. Based on the proposed hardware architecture, our method achieves compact implementations, which have low delay and high throughput. Experiment shows that compared with existing methods, the proposed method reduces register usage by about 10%.
|ホスト出版物のタイトル||International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT|
|出版ステータス||Published - 2008|
|イベント||2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing|
継続期間: 2008 10月 20 → 2008 10月 23
|Other||2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008|
|Period||08/10/20 → 08/10/23|
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