Automatic layout synthesis for FIR filters using a silicon compiler

Masaki Ishikawa, Masato Edahiro, Takeshi Yoshimura, Takashi Miyazaki, Shin ichi Aikoh, Takao Nishitani, Kaoru Mitsuhashi, Mitsuhiro Furuichi

研究成果: Conference contribution

8 引用 (Scopus)

抜粋

A silicon compiler for finite impulse response (FIR) filters is presented. The synthesis system takes as inputs only filter specifications and processing word lengths, and generates the FIR filter mask patterns in a few minutes. The system consists of two programs: an FIR filter design program to determine FIR filter coefficients at the minimal filter order to meet design objectives, and a module generator to generate mask patterns according to optimal parameters obtained by the filter design program. For describing layout structures correctly and easily, the module generator provides graphical layout description tools, and includes mechanisms to permit designing the structures before leaf-cells are completed. Layouts for several filters which have been successfully generated in a short time are described. A system-generated single-chip VLSI chrominance-luminance separator for NTSC composite TV signals using four FIR filters is shown.

元の言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
出版者Publ by IEEE
ページ2588-2591
ページ数4
4
出版物ステータスPublished - 1990
外部発表Yes
イベント1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
継続期間: 1990 5 11990 5 3

Other

Other1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4)
New Orleans, LA, USA
期間90/5/190/5/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • これを引用

    Ishikawa, M., Edahiro, M., Yoshimura, T., Miyazaki, T., Aikoh, S. I., Nishitani, T., Mitsuhashi, K., & Furuichi, M. (1990). Automatic layout synthesis for FIR filters using a silicon compiler. : Proceedings - IEEE International Symposium on Circuits and Systems (巻 4, pp. 2588-2591). Publ by IEEE.