Behavior-Aware cache hierarchy optimization for low-power multi-core embedded systems

Huatao Zhao*, Xiao Luo, Chen Zhu, Takahiro Watanabe, Tianbo Zhu


研究成果: Article査読

1 被引用数 (Scopus)


In modern embedded systems, the increasing number of cores requires efficient cache hierarchies to ensure data throughput, but such cache hierarchies are restricted by their tumid size and interference accesses which leads to both performance degradation and wasted energy. In this paper, we firstly propose a behavior-Aware cache hierarchy (BACH) which can optimally allocate the multi-level cache resources to many cores and highly improved the efficiency of cache hierarchy, resulting in low energy consumption. The BACH takes full advantage of the explored application behaviors and runtime cache resource demands as the cache allocation bases, so that we can optimally configure the cache hierarchy to meet the runtime demand. The BACH was implemented on the GEM5 simulator. The experimental results show that energy consumption of a three-level cache hierarchy can be saved from 5.29% up to 27.94% compared with other key approaches while the performance of the multi-core system even has a slight improvement counting in hardware overhead.

ジャーナルModern Physics Letters B
出版ステータスPublished - 2017 7月 30

ASJC Scopus subject areas

  • 統計物理学および非線形物理学
  • 凝縮系物理学


「Behavior-Aware cache hierarchy optimization for low-power multi-core embedded systems」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。