TY - GEN
T1 - Binary Neural Network in Robotic Manipulation
T2 - 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2021
AU - Ohara, Satoshi
AU - Ogata, Tetsuya
AU - Awano, Hiromitsu
N1 - Funding Information:
ACKNOWLEDGMENT This work was partially supported by JST, PRESTO Grant No. JP-MJPR18M1, JSPS KAKENHI Grant No. 21H03409.
Funding Information:
*This work was supported by JST, PRESTO Grant No. JP-MJPR18M1.
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - A neural network based flexible object manipulation system for a humanoid robot on FPGA is proposed. Although the manipulations of flexible objects using robots attract ever increasing attention since these tasks are the basic and essential activities in our daily life, it has been put into practice only recently with the help of deep neural networks. However such systems have relied on GPU accelerators, which cannot be implemented into the space limited robotic body. Although field programmable gate arrays (FPGAs) are known to be energy efficient and suitable for embedded systems, the model size should be drastically reduced since FPGAs have limited on-chip memory. To this end, we propose partially binarized deep convolutional auto-encoder technique, where only an encoder part is binarized to compress model size without degrading the inference accuracy. The model implemented on Xilinx ZCU102 achieves 41.1 frames per second with a power consumption of 3.1 W, which corresponds to 10× and 3.7× improvements from the systems implemented on Core i7 6700K and RTX 2080 Ti, respectively.
AB - A neural network based flexible object manipulation system for a humanoid robot on FPGA is proposed. Although the manipulations of flexible objects using robots attract ever increasing attention since these tasks are the basic and essential activities in our daily life, it has been put into practice only recently with the help of deep neural networks. However such systems have relied on GPU accelerators, which cannot be implemented into the space limited robotic body. Although field programmable gate arrays (FPGAs) are known to be energy efficient and suitable for embedded systems, the model size should be drastically reduced since FPGAs have limited on-chip memory. To this end, we propose partially binarized deep convolutional auto-encoder technique, where only an encoder part is binarized to compress model size without degrading the inference accuracy. The model implemented on Xilinx ZCU102 achieves 41.1 frames per second with a power consumption of 3.1 W, which corresponds to 10× and 3.7× improvements from the systems implemented on Core i7 6700K and RTX 2080 Ti, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85124366192&partnerID=8YFLogxK
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U2 - 10.1109/IROS51168.2021.9636825
DO - 10.1109/IROS51168.2021.9636825
M3 - Conference contribution
AN - SCOPUS:85124366192
T3 - IEEE International Conference on Intelligent Robots and Systems
SP - 6010
EP - 6015
BT - IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 27 September 2021 through 1 October 2021
ER -