Bipolar transistor with a buried layer formed by high-energy ion implantation for subhalf-micron bipolar-complementary metal oxide semiconductor LSIs

Takashi Kuroi, Youji Kawasaki, Yoshiyuki Ishigaki, Yasushi Kinoshita, Masahide Inuishi, Katsuhiro Tsukamoto, Natsuro Tsubouchi

研究成果: Article

2 引用 (Scopus)

抄録

We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BVCE0 —5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.

元の言語English
ページ(範囲)541-545
ページ数5
ジャーナルJapanese Journal of Applied Physics
33
発行部数1
DOI
出版物ステータスPublished - 1994
外部発表Yes

Fingerprint

large scale integration
Bipolar transistors
bipolar transistors
Ion implantation
ion implantation
CMOS
Fabrication
fabrication
Rapid thermal annealing
Cutoff frequency
Metals
Leakage currents
implantation
leakage
cut-off
damage
Silicon
annealing
energy
silicon

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)
  • Physics and Astronomy (miscellaneous)

これを引用

Bipolar transistor with a buried layer formed by high-energy ion implantation for subhalf-micron bipolar-complementary metal oxide semiconductor LSIs. / Kuroi, Takashi; Kawasaki, Youji; Ishigaki, Yoshiyuki; Kinoshita, Yasushi; Inuishi, Masahide; Tsukamoto, Katsuhiro; Tsubouchi, Natsuro.

:: Japanese Journal of Applied Physics, 巻 33, 番号 1, 1994, p. 541-545.

研究成果: Article

Kuroi, Takashi ; Kawasaki, Youji ; Ishigaki, Yoshiyuki ; Kinoshita, Yasushi ; Inuishi, Masahide ; Tsukamoto, Katsuhiro ; Tsubouchi, Natsuro. / Bipolar transistor with a buried layer formed by high-energy ion implantation for subhalf-micron bipolar-complementary metal oxide semiconductor LSIs. :: Japanese Journal of Applied Physics. 1994 ; 巻 33, 番号 1. pp. 541-545.
@article{7150cd09260648299887e9233beba108,
title = "Bipolar transistor with a buried layer formed by high-energy ion implantation for subhalf-micron bipolar-complementary metal oxide semiconductor LSIs",
abstract = "We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BVCE0 —5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.",
keywords = "Annealing, BiCMOS, Bipolar transistor, High-energy ion implantation, Junction leakage current, Silicon",
author = "Takashi Kuroi and Youji Kawasaki and Yoshiyuki Ishigaki and Yasushi Kinoshita and Masahide Inuishi and Katsuhiro Tsukamoto and Natsuro Tsubouchi",
year = "1994",
doi = "10.1143/JJAP.33.541",
language = "English",
volume = "33",
pages = "541--545",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "1",

}

TY - JOUR

T1 - Bipolar transistor with a buried layer formed by high-energy ion implantation for subhalf-micron bipolar-complementary metal oxide semiconductor LSIs

AU - Kuroi, Takashi

AU - Kawasaki, Youji

AU - Ishigaki, Yoshiyuki

AU - Kinoshita, Yasushi

AU - Inuishi, Masahide

AU - Tsukamoto, Katsuhiro

AU - Tsubouchi, Natsuro

PY - 1994

Y1 - 1994

N2 - We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BVCE0 —5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.

AB - We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BVCE0 —5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.

KW - Annealing

KW - BiCMOS

KW - Bipolar transistor

KW - High-energy ion implantation

KW - Junction leakage current

KW - Silicon

UR - http://www.scopus.com/inward/record.url?scp=0028319460&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028319460&partnerID=8YFLogxK

U2 - 10.1143/JJAP.33.541

DO - 10.1143/JJAP.33.541

M3 - Article

AN - SCOPUS:0028319460

VL - 33

SP - 541

EP - 545

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 1

ER -