Bit-length optimization method for high-level synthesis based on non-linear programming technique

Nobuhiro Doi*, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura

*この研究の対応する著者

研究成果: Article査読

3 被引用数 (Scopus)

抄録

High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.

本文言語English
ページ(範囲)3427-3434
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
DOI
出版ステータスPublished - 2006 12

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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