Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Nobuhiro Doi*, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe

*この研究の対応する著者

研究成果査読

1 被引用数 (Scopus)

抄録

In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.

本文言語English
ページ(範囲)3184-3191
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E86-A
12
出版ステータスPublished - 2003 12

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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