Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder

Chen Xianmin*, Liu Peilin, Zhu Jiayi, Zhou Dajiang, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%-78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.

本文言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
ページ1069-1072
ページ数4
DOI
出版ステータスPublished - 2009
外部発表はい
イベント2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei
継続期間: 2009 5 242009 5 27

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CityTaipei
Period09/5/2409/5/27

ASJC Scopus subject areas

  • 電子工学および電気工学

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