Buffer planning for 3D ICs

Sheqin Dong*, Hongjie Bai, Xianlong Hong, Satoshi Goto

*この研究の対応する著者

    研究成果: Conference contribution

    4 被引用数 (Scopus)

    抄録

    With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. 3D integration, which stacks multiple device layers, greatly reduces interconnect delay. Buffer insertion, as another approach to reduce wire delay, is still necessary to further optimize interconnects. In this paper, a buffer planning algorithm at floorplanning stage for 3D ICs is proposed. Firstly, we reduce buffer insertion to a dynamic programming path problem. Then we show its potential to handle the 3D buffer insertion problem. At the same time, vertical interlayer vias are also planned. At last, buffer planning is integrated with floorplanning to optimize the packing so that not only area and wire length reach a satisfying value, timing performance is also optimized.

    本文言語English
    ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
    ページ1735-1738
    ページ数4
    DOI
    出版ステータスPublished - 2009
    イベント2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei
    継続期間: 2009 5 242009 5 27

    Other

    Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
    CityTaipei
    Period09/5/2409/5/27

    ASJC Scopus subject areas

    • 電子工学および電気工学

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