With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. 3D integration, which stacks multiple device layers, greatly reduces interconnect delay. Buffer insertion, as another approach to reduce wire delay, is still necessary to further optimize interconnects. In this paper, a buffer planning algorithm at floorplanning stage for 3D ICs is proposed. Firstly, we reduce buffer insertion to a dynamic programming path problem. Then we show its potential to handle the 3D buffer insertion problem. At the same time, vertical interlayer vias are also planned. At last, buffer planning is integrated with floorplanning to optimize the packing so that not only area and wire length reach a satisfying value, timing performance is also optimized.
|ホスト出版物のタイトル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版ステータス||Published - 2009|
|イベント||2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei|
継続期間: 2009 5月 24 → 2009 5月 27
|Other||2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009|
|Period||09/5/24 → 09/5/27|
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