Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura

研究成果: Paper査読

4 被引用数 (Scopus)

抄録

To allow the application of floating silicon on insulator (SOI) technology on analog circuits, the full body-fixing structure can be used. However, this technique may cause some shortcomings in scalability and layout compatibility. The partial trench isolation (PTI) technique is proposed, in which the body potential is fixed through the region under the trench oxide. With the PTI technology, the floating-body effects are eliminated while maintaining SOI-inherent merits and scalable deep sub-quarter micron LSIs can be realized using accumulated bulk design properties without layout modification.

本文言語English
ページ131-132
ページ数2
出版ステータスPublished - 1999 12 1
外部発表はい
イベントThe 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference - Rohnert Park, CA, USA
継続期間: 1999 10 41999 10 7

Other

OtherThe 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference
CityRohnert Park, CA, USA
Period99/10/499/10/7

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル