Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Yuuichi Hirano, Shigenobu Maeda, Takuji Matsumoto, Koji Nii, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Hiroshi Kawashima, Shigeto Maegawa, Masahide Inuishi, Tadashi Nishimura

研究成果: Article査読

8 被引用数 (Scopus)

抄録

Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM was obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.

本文言語English
ページ(範囲)2816-2822
ページ数7
ジャーナルIEEE Transactions on Electron Devices
48
12
DOI
出版ステータスPublished - 2001 12 1
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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