As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks.
|ホスト出版物のタイトル||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|出版ステータス||Published - 2010|
|イベント||20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI|
継続期間: 2010 5月 16 → 2010 5月 18
|Other||20th Great Lakes Symposium on VLSI, GLSVLSI 2010|
|Period||10/5/16 → 10/5/18|
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