Bus via reduction based on floorplan revising

Ou He*, Sheqin Dong, Jinian Bian, Sotoshi Goto, Chung Kuan Cheng

*この研究の対応する著者

    研究成果: Conference contribution

    5 被引用数 (Scopus)

    抄録

    As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks.

    本文言語English
    ホスト出版物のタイトルProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
    ページ9-14
    ページ数6
    DOI
    出版ステータスPublished - 2010
    イベント20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI
    継続期間: 2010 5 162010 5 18

    Other

    Other20th Great Lakes Symposium on VLSI, GLSVLSI 2010
    CityProvidence, RI
    Period10/5/1610/5/18

    ASJC Scopus subject areas

    • 工学(全般)

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