BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Seung Ju Lee*, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). In this paper, A busmesh network-on-chip (BMNoC) architecture is proposed, together with simulation results. It is comprised of bus-based connection and global mesh routers to enhance the performance of on-chip communication. Furthermore, MPEG-4, H.264 and a hybrid application mixed MPEG-4 and H.264 on our architecture illustrates the better performance than earlier studies and feasibility of BMNoC.

本文言語English
ホスト出版物のタイトルProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
ページ712-715
ページ数4
DOI
出版ステータスPublished - 2010 12 1
イベント2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
継続期間: 2010 12 62010 12 9

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
国/地域Malaysia
CityKuala Lumpur
Period10/12/610/12/9

ASJC Scopus subject areas

  • 電子工学および電気工学

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