Cache miss reduction through hardware-assisted loop optimization

Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto

研究成果: Conference contribution

抄録

To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

本文言語English
ホスト出版物のタイトルProceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD
ページ129-134
ページ数6
1
DOI
出版ステータスPublished - 2008
イベント2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD - Xi'an
継続期間: 2008 4 162008 4 18

Other

Other2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD
CityXi'an
Period08/4/1608/4/18

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Human-Computer Interaction

フィンガープリント 「Cache miss reduction through hardware-assisted loop optimization」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル