抄録
To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD |
ページ | 129-134 |
ページ数 | 6 |
巻 | 1 |
DOI | |
出版ステータス | Published - 2008 |
イベント | 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD - Xi'an 継続期間: 2008 4 16 → 2008 4 18 |
Other
Other | 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD |
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City | Xi'an |
Period | 08/4/16 → 08/4/18 |
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Networks and Communications
- Human-Computer Interaction