Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.
|ホスト出版物のタイトル||2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings|
|出版ステータス||Published - 2006|
|イベント||2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin|
継続期間: 2006 6月 25 → 2006 6月 28
|Other||2006 International Conference on Communications, Circuits and Systems, ICCCAS|
|Period||06/6/25 → 06/6/28|
ASJC Scopus subject areas