Calculating the effective capacitance for interconnect loads based on thevenin model

Shuai Fang*, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

*この研究の対応する著者

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

    本文言語English
    ホスト出版物のタイトル2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
    ページ2474-2477
    ページ数4
    4
    DOI
    出版ステータスPublished - 2006
    イベント2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin
    継続期間: 2006 6 252006 6 28

    Other

    Other2006 International Conference on Communications, Circuits and Systems, ICCCAS
    CityGuilin
    Period06/6/2506/6/28

    ASJC Scopus subject areas

    • 電子工学および電気工学

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