Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough red brick wall emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems. In this paper, we investigate the practicality of a dense power-ground interconnect architecture developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

    本文言語English
    ホスト出版物のタイトルProceedings - International Symposium on Quality Electronic Design, ISQED
    ページ153-158
    ページ数6
    DOI
    出版ステータスPublished - 2005
    イベント6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA
    継続期間: 2005 3 212005 3 23

    Other

    Other6th International Symposium on Quality Electronic Design, ISQED 2005
    CitySan Jose, CA
    Period05/3/2105/3/23

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学
    • 安全性、リスク、信頼性、品質管理

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