Cell array design with row-driven source line in block shunt architecture applicable to future 6f2 1t1mtj memory

Tongshuang Huang, Takashi Ohsawa

研究成果: Conference contribution

抄録

In this paper, we propose a new 1T1MTJ cell array architecture with SL parallel to WL to achieve a small cell size, in which page mode write can be realized without performance degradation. We propose a row-driven source line (RSL) 1T1MTJ memory cell array architecture for minimizing the cell size and a corresponding operational waveform. A block shunt architecture (BSA) that shunts lower source line (LSL) and upper source line (USL) is proposed to make page mode write possible. Size of 1T1MTJ cell can be shrunk to 6F2 when the state-of-The-Art design rules are applied.

本文言語English
ホスト出版物のタイトル2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728109428
DOI
出版ステータスPublished - 2019 4
イベント2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan, Province of China
継続期間: 2019 4 222019 4 25

出版物シリーズ

名前2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
CountryTaiwan, Province of China
CityHsinchu
Period19/4/2219/4/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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