This paper presents luminance/chrominance (Y/C) separation and synthesis VLSI chips developed with an application-specific silicon compiler. The Y/C separation chip separates Y/C components from a 13.5-MHz sampled composite TV signal for a common intermediate format (CIF) video signal, by using a formula Omitteddown-sampled luminance signal (Y) and two formula Omitted downsampled color-difference signals (CR, CB). The Y/C synthesis chip synthesizes the composite signal from Y, CR, and CB. In order to develop compact chips, three different FIR filter structures, such as a filter with symmetric coefficients, a decimator, and an interpolator, are first designed to have a minimum number of multiply-adders. In addition to these filter structures, multipliers in the filters are newly designed by using canonical signed-digit representation (CSR) for filter coefficients. Restriction of the number of nonzero digits in the CSR leads to reduction in number of adder units in the multiplier and its compact realization. The structures of the filters and the CSR multipliers are then employed as a design database of the silicon compiler. The silicon compiler provides a filter design environment considering usage of the CSR multipliers. Therefore, FIR filter modules with the desired filter specifications are automatically generated. The optimized filter and CSR multiplier structures allow the Y/C separation chip with an FIR filter and three FIR decimators to be implemented in a 10.4 × 11.7 mm2 area, using 1.2 μm CMOS technology. The Y/C synthesis chip with three FIR interpolators is also fabricated in a 10.8 ×11.8 mm2 die size. These chips help to develop compact and cost-effective video systems, such as TV conference systems and TV phones.
|ジャーナル||IEEE Transactions on Circuits and Systems for Video Technology|
|出版ステータス||Published - 1992 6月|
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