Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high‐speed, low soft error rate and low power consumption. As a result of applying it to a 5‐V 16‐K MOS (D) RAM, a performance index of 0.6 pJ/bit and soft error rate of 4 × 107 device. hours are obtained. The adequacy of the modified scaling law is examined by considering a 12‐V 16‐K MOS (D) RAM with scaling constant k = 1 and a 5‐V 16‐K MOS (D) RAM with k = 2. It is shown that circuit design with consideration of soft error cannot achieve large improvement of the performance index of high‐capacity MOS (D) RAM and that the soft error is an impediment to high‐performance MOS (D) RAM.
|ジャーナル||Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|出版ステータス||Published - 1982|
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering