Circuit partitioning algorithm with replication capability for multi-FPGA systems

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

研究成果: Article査読

2 被引用数 (Scopus)

抄録

An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

本文言語English
ページ(範囲)1765-1776
ページ数12
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E78-A
12
出版ステータスPublished - 1995 12 1

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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