An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.
|ジャーナル||IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences|
|出版ステータス||Published - 1995 12 1|
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics