Clock buffer placement algorithm for wire-delay-dominated timing model

M. Edahiro*, R. J. Lipton


研究成果: Conference article査読

4 被引用数 (Scopus)


A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.

ジャーナルProceedings of the IEEE Great Lakes Symposium on VLSI
出版ステータスPublished - 1996
イベントProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA
継続期間: 1996 3月 221996 3月 23

ASJC Scopus subject areas

  • 電子工学および電気工学


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