TY - JOUR
T1 - Clock buffer placement algorithm for wire-delay-dominated timing model
AU - Edahiro, M.
AU - Lipton, R. J.
PY - 1996
Y1 - 1996
N2 - A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.
AB - A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.
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M3 - Conference article
AN - SCOPUS:0029708404
SP - 143
EP - 147
JO - Proceedings of the IEEE Great Lakes Symposium on VLSI
JF - Proceedings of the IEEE Great Lakes Symposium on VLSI
SN - 1066-1395
T2 - Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI
Y2 - 22 March 1996 through 23 March 1996
ER -