A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.
|ジャーナル||Proceedings of the IEEE Great Lakes Symposium on VLSI|
|出版ステータス||Published - 1996|
|イベント||Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA|
継続期間: 1996 3月 22 → 1996 3月 23
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