Clocked CMOS adiabatic logic with low-power dissipation

He Li, Yimeng Zhang, Tsutomu Yoshihara

    研究成果: Conference contribution

    7 引用 (Scopus)

    抄録

    This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

    元の言語English
    ホスト出版物のタイトルISOCC 2013 - 2013 International SoC Design Conference
    出版者IEEE Computer Society
    ページ64-67
    ページ数4
    ISBN(印刷物)9781479911417
    DOI
    出版物ステータスPublished - 2013
    イベント2013 International SoC Design Conference, ISOCC 2013 - Busan
    継続期間: 2013 11 172013 11 19

    Other

    Other2013 International SoC Design Conference, ISOCC 2013
    Busan
    期間13/11/1713/11/19

    Fingerprint

    Energy dissipation
    Recovery
    Energy efficiency
    Clocks

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    これを引用

    Li, H., Zhang, Y., & Yoshihara, T. (2013). Clocked CMOS adiabatic logic with low-power dissipation. : ISOCC 2013 - 2013 International SoC Design Conference (pp. 64-67). [6863986] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863986

    Clocked CMOS adiabatic logic with low-power dissipation. / Li, He; Zhang, Yimeng; Yoshihara, Tsutomu.

    ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 64-67 6863986.

    研究成果: Conference contribution

    Li, H, Zhang, Y & Yoshihara, T 2013, Clocked CMOS adiabatic logic with low-power dissipation. : ISOCC 2013 - 2013 International SoC Design Conference., 6863986, IEEE Computer Society, pp. 64-67, 2013 International SoC Design Conference, ISOCC 2013, Busan, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6863986
    Li H, Zhang Y, Yoshihara T. Clocked CMOS adiabatic logic with low-power dissipation. : ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society. 2013. p. 64-67. 6863986 https://doi.org/10.1109/ISOCC.2013.6863986
    Li, He ; Zhang, Yimeng ; Yoshihara, Tsutomu. / Clocked CMOS adiabatic logic with low-power dissipation. ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. pp. 64-67
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