Clocked CMOS adiabatic logic with low-power dissipation

He Li, Yimeng Zhang, Tsutomu Yoshihara

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

    本文言語English
    ホスト出版物のタイトルISOCC 2013 - 2013 International SoC Design Conference
    出版社IEEE Computer Society
    ページ64-67
    ページ数4
    ISBN(印刷版)9781479911417
    DOI
    出版ステータスPublished - 2013
    イベント2013 International SoC Design Conference, ISOCC 2013 - Busan
    継続期間: 2013 11 172013 11 19

    Other

    Other2013 International SoC Design Conference, ISOCC 2013
    CityBusan
    Period13/11/1713/11/19

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

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