CMOS low-power subthreshold reference voltage utilizing self-biased body effect

Hao Zhang*, Yimeng Zhang, Mengshu Huang, Yoshihara Tsutomu

*この研究の対応する著者

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025%/V and 0.0019%/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2.

    本文言語English
    ホスト出版物のタイトルProceedings of International Conference on ASIC
    ページ516-519
    ページ数4
    DOI
    出版ステータスPublished - 2011
    イベント2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
    継続期間: 2011 10 252011 10 28

    Other

    Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
    CityXiamen
    Period11/10/2511/10/28

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

    フィンガープリント

    「CMOS low-power subthreshold reference voltage utilizing self-biased body effect」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル