抄録
A design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1. 2-1. 4 times larger than that resulting from manual layouts. It is concluded that this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.
本文言語 | English |
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ページ(範囲) | 374-382 |
ページ数 | 9 |
ジャーナル | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
巻 | CAD-6 |
号 | 3 |
出版ステータス | Published - 1987 5月 |
外部発表 | はい |
ASJC Scopus subject areas
- 計算理論と計算数学
- コンピュータ サイエンスの応用
- ハードウェアとアーキテクチャ
- 電子工学および電気工学