抄録
A design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1. 2-1. 4 times larger than that resulting from manual layouts. It is concluded that this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 374-382 |
| ページ数 | 9 |
| ジャーナル | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| 巻 | CAD-6 |
| 号 | 3 |
| 出版ステータス | Published - 1987 5 |
| 外部発表 | はい |
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Computer Science Applications
- Hardware and Architecture
- Electrical and Electronic Engineering