A new design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that the resulting chip size is only 1. 2-1. 4 times larger than that resulting from manual layout. Therefore, this compaction-based custom LSI layout method is effective for achieving a minimal chip layout design.
|ホスト出版物のタイトル||Unknown Host Publication Title|
|出版場所||New York, NY, USA|
|出版物ステータス||Published - 1985|
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