COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD.

Masaki Ishikawa, Tsuneo Matsuda, Satoshi Goto

    研究成果: Conference contribution

    2 引用 (Scopus)

    抜粋

    A new design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that the resulting chip size is only 1. 2-1. 4 times larger than that resulting from manual layout. Therefore, this compaction-based custom LSI layout method is effective for achieving a minimal chip layout design.

    元の言語English
    ホスト出版物のタイトルUnknown Host Publication Title
    出版場所New York, NY, USA
    出版者IEEE
    ページ343-345
    ページ数3
    ISBN(印刷物)0818606878
    出版物ステータスPublished - 1985

      フィンガープリント

    ASJC Scopus subject areas

    • Engineering(all)

    これを引用

    Ishikawa, M., Matsuda, T., & Goto, S. (1985). COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD.Unknown Host Publication Title (pp. 343-345). IEEE.