COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD.

Masaki Ishikawa*, Tsuneo Matsuda, Satoshi Goto

*この研究の対応する著者

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    A new design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that the resulting chip size is only 1. 2-1. 4 times larger than that resulting from manual layout. Therefore, this compaction-based custom LSI layout method is effective for achieving a minimal chip layout design.

    本文言語English
    ホスト出版物のタイトルUnknown Host Publication Title
    Place of PublicationNew York, NY, USA
    出版社IEEE
    ページ343-345
    ページ数3
    ISBN(印刷版)0818606878
    出版ステータスPublished - 1985

    ASJC Scopus subject areas

    • 工学(全般)

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