Comparison of preemption schemes for partially reconfigurable FPGAs

Krzysztof Jozwik*, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

*この研究の対応する著者

研究成果: Article査読

15 被引用数 (Scopus)

抄録

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization.

本文言語English
論文番号6179510
ページ(範囲)45-48
ページ数4
ジャーナルIEEE Embedded Systems Letters
4
2
DOI
出版ステータスPublished - 2012
外部発表はい

ASJC Scopus subject areas

  • 制御およびシステム工学
  • コンピュータ サイエンス(全般)

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