Compressor tree based processing element optimization in propagate partial SAD architecture

Yiqing Huang*, Liu Qin, Takeshi Ikenaga

*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

In H.264/AVC standard, the improvement of motion estimation (ME) part helps to enhance the performance greatly. However, the ME part, especially the integer motion estimation (IME) occupies computation complexity dramatically, which leads to complexity in hardware implementation. Many works have been done to achieve efficient IME engine and propagate partial SAD (PPSAD) architecture is the most efficient one in data path and hardware cost. Based on PPSAD structure, this paper proposes a compressor tree based compact PE array architecture. The 4-2 and 3-2 compressor trees are used to build up this compact structure. The proposed structure is embedded into PPSAD architecture and synthesized under different frequency points. With TSMC 0.18μm 1P8M technology, the proposed architecture can achieve 10%-13% hardware cost reduction for asingle4×4 PE array compared with most recent work. About 10.7k, 13.2k and 6.5k gates hardware cost can be saved compared with previous PPSAD structures.

本文言語English
ホスト出版物のタイトルProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
ページ1786-1789
ページ数4
DOI
出版ステータスPublished - 2008
イベントAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
継続期間: 2008 11月 302008 12月 3

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
国/地域China
CityMacao
Period08/11/3008/12/3

ASJC Scopus subject areas

  • 電子工学および電気工学

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