Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

In this paper, a concurrent faulty clock detection method is proposed for crypto circuits against clock glitch based differential fault analysis (DFA). In the proposed method, a nonlogic buffer-based delay chain is inserted, and then by monitoring the delay along the delay chain, a possible clock glitch based DFA can be detected. Experimental results on an AES circuit show that the proposed method can successfully detect clock glitch based attacks, and the required area overhead is only 0.47% that is much smaller than previous works.

本文言語English
ホスト出版物のタイトル2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
ページ1432-1435
ページ数4
DOI
出版ステータスPublished - 2013
イベント2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
継続期間: 2013 5 192013 5 23

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
国/地域China
CityBeijing
Period13/5/1913/5/23

ASJC Scopus subject areas

  • 電子工学および電気工学

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