抄録
As VLSI design complexity continues to increase, the yield loss due to via failure becomes more and more significant. Redundant via insertion is highly recommended for improving chip yield and reliability. In this paper, we study the redundant via insertion problem in a post-routing stage, where a single via can have at most one redundant via inserted next to it .The goal is to insert as many redundant vias as possible and, at the same time, try to equilibrate the via density, which is good for the via density rules. We propose a convex-cost flow based approach to solve the problem within up to three routing layers. The experimental results show that, the proposed method can produce optimal solutions on defined density grid structure with maximum redundant via insertion, and achieve an at least 32.61% improvement of via density equalization.
本文言語 | English |
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ホスト出版物のタイトル | ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC |
ページ | 1280-1283 |
ページ数 | 4 |
DOI | |
出版ステータス | Published - 2009 |
イベント | 2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha 継続期間: 2009 10月 20 → 2009 10月 23 |
Other
Other | 2009 8th IEEE International Conference on ASIC, ASICON 2009 |
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City | Changsha |
Period | 09/10/20 → 09/10/23 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学